1. Field of the Invention
The present invention relates to an output circuit for a bus driver integrated circuit and, more particularly, to a control-stage circuit of a Bi-MOS integrated circuit having both bipolar (Bi) and metal oxide semiconductor (MOS) elements.
2. Description of the Related Art
In a conventional Bi-MOS output circuit for outputting a signal of a TTL (Transistor Transistor Logic) level, a bipolar transistor in the output-stage circuit is controlled by a MOS transistor in a control-stage circuit. A typical example is shown in FIG. 1. In the control-stage circuit of this output circuit, an input terminal IN for receiving an input signal is connected to the gate of an n-channel MOS transistor M1 for phase division. The drain of the MOS transistor M1 is connected to a power source Vcc through a resistor R1. The source of the MOS transistor M1 is connected to a ground potential GND through a pull down circuit PD. In this output-stage circuit, a pull up npn transistor Q2 and a pull down Schottky barrier npn transistor Q3 are connected in a totem pole scheme between the power source Vcc and the ground potential GND. A common node between the transistors Q2 and Q3 is connected to an output terminal OUT.
A resistor R2 is connected between the collector of the pull up npn transistor Q2 and the power source Vcc, and a resistor R3 is connected in a base-emitter path of the transistor Q2. The base of the npn transistor Q3 is connected to the pull down circuit PD. A Schottky barrier npn transistor Q1 is Darlington-connected to the npn transistor Q2. The base of the npn transistor Q1 is connected to the drain of a MOS transistor M1. A first Schottky barrier diode D1 is connected between the emitter of the npn transistor Q1 and the drain of the MOS transistor M1. A second Schottky barrier diode D2 is connected between the output terminal OUT and the drain of the MOS transistor M1.
Note that the transistors Q1 and Q3 and the diodes D1 and D2 are of a Schottky barrier type, but they are not limited to this.
An operation of the output circuit having the arrangement described above will be described below. When an input signal input to the input terminal IN goes from level "1" to level "0", the MOS transistor M1 is turned off. A base current is supplied from the power source Vcc to the npn transistor Q1 through the resistor R1, so that the transistor Q1 is turned on, and at the same time, the pull up npn transistor Q2 is also turned on. Meanwhile, since the MOS transistor M1 is turned off, the base charge of the pull down npn transistor Q3 is extracted through the pull down circuit PD, so that the npn transistor Q3 is turned off. In this manner, when the npn transistor Q1 is turned on and the npn transistor Q3 is turned off, a current is supplied from the power source Vcc to the output terminal OUT through the resistor R2 and the npn transistor Q2. An output voltage at the output terminal OUT is changed from TTL level "0" to TTL level "1". In this case, since the first and second diodes D1 and D2 are kept off, this change in output level does not influence the operation of the circuit.
However, when the input signal supplied to the input terminal IN goes from CMOS level "0" to CMOS level "1", the MOS transistor M1 is turned on. A base current is supplied from the power source Vcc to the pull down npn transistor Q3 through the resistor R1 and the MOS transistor M1, and at the same time, a base current is also supplied from the output terminal OUT to the transistor Q3 through the second diode D2, so that the transistor Q3 is turned on. Meanwhile, since the MOS transistor M1 is turned on, the base charges of the npn transistors Q1 and Q2 are extracted by the MOS transistor M1, so that the npn transistors Q1 and Q2 are turned off. In this case, the base charge of the npn transistor Q2 is rapidly extracted by the first diode D1, and the transistor Q2 is quickly turned off. Potentials at both terminals of the resistor R3 are set to be equal to each other by the first and second diodes D1 and D2, and the pull up transistor Q2 is accurately turned off. Therefore, the charge at the output terminal OUT is extracted to the ground potential through the pull down npn transistor Q3, and the output voltage goes from TTL level "1" to TTL level "0".
It is desirable to increase a load drive capacity of the output circuit upon a change in output voltage of the output circuit from level "1" to level "0", i.e., a load drive capacity of the transistor Q3 so as to drive a large load circuit. For this purpose, the resistance of the resistor R1 is minimized, and the base current of the pull down npn transistor Q3 is increased in a conventional arrangement. When the resistance of the resistor R1 is decreased, a leading edge of an output waveform upon a change in output voltage of the output circuit from level "0" to level "1" becomes steep, and the rise time of the output waveform is shortened. That is, when the input signal supplied to the input terminal IN goes from CMOS level "1" to CMOS level "0" to turn off the MOS transistor M1, and when the pull up npn transistors Q1 and Q2 are turned on to change the output voltage of the output circuit from level "0" to level "1", the base potential of the pull up npn transistor Q1 is changed in accordance with a time constant determined by a parasitic base capacitance and the resistor R1 if its base current is neglected. When the resistance of the resistor R1 is reduced, a rate of change in base potential of the transistor Q1 is increased, and the rise time of the output waveform in response to the input signal is shortened. Therefore, the rise time of the output waveform is shortened.
When the resistance of the resistor R1 is decreased, the load drive capacity of the pull down npn transistor Q3 is increased upon a change in output voltage of the output circuit from level "1" to level "0", as described above. However, since the load drive capacity of the transistor Q3 is increased, a large transient current (sink current) flows from a load circuit (not shown) to the output terminal OUT upon this change in output level. When the large sink current transiently flows upon a change in output level of the output circuit (i.e., a change in output level of the integrated circuit), a large voltage drop transiently occurs in an inductance present in a lead or the like of an integrated circuit package, thereby increasing switching noise.
A sink current i of the integrated circuit is represented as follows: EQU i=C.multidot.dV/dt
where C is the load capacitance of the integrated circuit and dV/dt is a slewing rate of the output waveform of the integrated circuit. A voltage drop .DELTA.V caused by the transient sink current is given as follows: ##EQU1## where L is the inductance existing in a lead or the like of the integrated circuit package. Switching noise corresponding to the voltage drop .DELTA.V is generated by a transient sink current.
In the conventional Bi-CMOS output circuit, the load drive capacity of the pull down npn transistor is increased to increase a load drive capacity upon a change in output voltage of the output circuit from level "1" to level "0". For this reason, a large transient sink current flows to generate switching noise upon a change in output voltage of the output circuit from level "1" to level "0".